The present invention relates to a bus driving and decoding circuit for data processing systems.
In modern data processing systems, the bus architecture is widely used.
A plurality of active units, central processors or data input/output controllers, collectively referred to as processors may get access to a plurality of passive resources, such as memories, register banks or peripheral units, through a common bus, comprising a plurality of leads, over which each processor may put, in time sharing, addresses and commands to forward data and commands to a selected unit and to receive from it data and status signals.
The bus constitutes a shared communication path which must be used with the utmost efficiency, by reducing to a minimum the information transfer time with the twofold objective of increasing the individual processors performance in the information transfer, and of minimizing the processor contention in bus access.
At the state of the art and with components readily available on the market, the information exchange occurs with procedures which develop in the span of a few hundreds of nanoseconds.
It is therefore clear that reducing the information transfer time by a few tens of nanoseconds contributes to improve the system performances in a relevant way.
A further aspect to be considered is the fast evolution of electronic technology. Due to this fast evolution it is desirable to design and implement computer systems capable of accepting and using new components, generally faster, in order to increase system performance without requiring a substantial redesign of the product.